PIC16F74T-E/ML【PDF 11/104 页】IC MCU FLASH 4KX14 A/D 44QFN

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Sheet目录3882

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2009 Microchip Technology Inc.

DS39682E-page 161

PIC18F45J10 FAMILY

REGISTER 16-4:

SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C MODE)

R/W-0

WCOL

SSPOV

SSPEN(1)

CKP

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

WCOL:

Write Collision Detect bit

In Master Transmit mode:

= A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a

transmission to be started (must be cleared in software)

= No collision

In Slave Transmit mode:

= The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in

software)

= No collision

In Receive mode (Master or Slave modes):

This is a “don’t care” bit.

bit 6

SSPOV:

Receive Overflow Indicator bit

In Receive mode:

= A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in

software)

= No overflow

In Transmit mode:

This is a “don’t care” bit in Transmit mode.

bit 5

SSPEN:

Master Synchronous Serial Port Enable bit(1)

= Enables the serial port and configures the SDAx and SCLx pins as the serial port pins

= Disables serial port and configures these pins as I/O port pins

bit 4

CKP:

SCK Release Control bit

In Slave mode:

= Release clock

= Holds clock low (clock stretch), used to ensure data setup time

In Master mode:

Unused in this mode.

bit 3-0

SSPM<3:0>:

Synchronous Serial Port Mode Select bits

1111

= I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

1110

= I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

1011

= I2C Firmware Controlled Master mode (slave Idle)

1000

= I2C Master mode, clock = FOSC/(4 * (SSPxADD + 1))

0111

= I2C Slave mode, 10-bit address

0110

= I2C Slave mode, 7-bit address

Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.

Note 1:

When enabled, the SDAx and SCLx pins must be configured as inputs.

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